module Registers_block ( RS, WR, EN, DATA_IN, Decimation, Trigger_level_A, Trigger_level_B, WIN, cnfPin ); //Декларируем внешние сигналы input [7:0] DATA_IN; input [15:0] EN; input RS; input WR; output [15:0] Decimation; output [7:0] Trigger_level_A; output [7:0] Trigger_level_B; output [15:0] WIN; output [7:0] cnfPin; reg[15:0] Decimation; reg[7:0] Trigger_level_A; reg[7:0] Trigger_level_B; reg[15:0] WIN; reg[7:0] cnfPin; //------------------------------------------------- always @(posedge WR) begin // if(RS == 0) begin case (EN) 16'b0000000000000000: Decimation[7:0] <= DATA_IN; 16'b0000000000000001: Decimation[15:8] <= DATA_IN; 16'b0000000000000010: Trigger_level_A <= DATA_IN; 16'b0000000000000100: Trigger_level_B <= DATA_IN; 16'b0000000000001000: WIN[7:0] <= DATA_IN; 16'b0000000000010000: WIN[15:8] <= DATA_IN; 16'b0000000000100000: cnfPin <= DATA_IN; default; endcase end end //always endmodule